@Chad-Sweet More on this from the manufacturer:
MIPI Protocol
The product we use is 2lane MIPI. The MIPI interface includes 1 pair of source-synchronized differencing clocks and 2 pairs of differencing data lines clock signals, which enter the high-speed mode at the beginning of each frame and exit the high-speed mode at the end of each frame. The interframe is in low power mode (both data and clock line are at 1.2V high level). MINI2-640, for example, uses a clock frequency of 400MHz. The data line sends the start packet of each frame at the beginning and the end packet of each frame at the end. The number of long packets between the start and end packets of each frame is the same as the height value of the array (such as a 640 * 512 module with 512 long packets), and each long packet data contains row valid data.