Hi @scosgrove,
Thanks for the details.
On the DSP there is a dedicated HW block for each UART (similar for the UARTs connected to the application processor). All the UARTs supported on DSP have hardware FIFOs. Since you asked about the size:
DSP UART2 has 64-byte low level FIFO on RX DSP UART6, 7 have 128-byte low level FIFO on RXWhen fifo is close to filling up, there is an ISR that triggers on the DSP which transfers the data from FIFO to other memory, and then the data propagates to the user. I wonder if there is some issue when fifo is read while another byte is incoming into fifo at the same time.
Which uart port are you using for this test?
I can do some testing with bursts of 70-250 byte packets. In the past we have tested continuous data transfers of several KB but not at high rates. Also, what baud rate are you using now?
Alex